High Rate APPS and Bi-APPS LDPC Codes Design with Low Error Floor and Large Girth

摘要

In this paper, two new methods to construct low-density parity-check (LDPC) codes with low error floor and large girth are proposed. The first one is APPS-LDPC codes based on Arithmetic Progression theory and cycle classification, whose girth is at least eight. Based on the designed APPS-LDPC codes, we further construct Bi-diagonal APPS-LDPC codes with column degree 4, whose circulant permutation matrix is combined by two shifted identity matrix. The designed APPS-LDPC code has 0.25 and 0.2 dB coding gain compared to partition-and-shift (PS)-LDPC code and progressive-edge-growth (PEG)-LDPC code. And the Bi-APPS-LDPC code has similar performance to T2 LDPC code in CCSDS standard, but its effective structure is more suitable for high throughput decoder implementation on FPGA. Both codes have less construction complexity than PS-LDPC code and PEG-LDPC code.