High Performance and Flexible Configuration Data Acquisition and Processing Unit in All Digital PET System

摘要

Introduction: This paper presents a software-based data acquisition and processing unit (DAPU) architecture for an all-digital positron emission tomography (PET) system based on 352 LYSO/ SiPM detectors with local digitization. By obtaining raw data directly from individual detectorvia 10-Gigabit Ethernet in UDP protocol, a self-adapting calibration method for PET is proposed. The architecture is designed to be scalable across an Ethernet network as well as for multi-CPU computer systems. Besides that, more accurate and computationally complex, iterative algorithms couldbe employed and easily reformed with flexible configuration in DAPU for higher quality and accurate PET image. Background: By comparison with the traditional PET detector module, which outputs singles or coincidences, the detector module in all digital PET system outputs raw detectordata in UDP sockets directly, including digitized timestamps and identifiers of triggered SiPM pixels. To obtain the detector raw data, a high bandwidth data transmission system is required. Objective: The aim was to present a high performance data acquisition unit to collect and processthe digital data of the original flash pulse in order to meet real-time data acquisition and processing of the digital PET system. Methods: A software based data acquisition and processing unit for digital PET system is presented, which is based on SiPM detector coupled with LYSO crystalarrays. The data acquisition and processing server (DAPS) receives detector raw data and outputs coincidence data by using memory cache and parallel computing. Results: Due to the use of cache and parallel computing, the result of experiment shows that it is possible to acquire and processthe detector raw data simultaneously even the data rate is as high as 1Gbps. Conclusion: A software based data acquisition and processing unit meets the needs of data acquisition in digital PET system by using memory cache and parallel computing.