Synthesis of Asynchronous Interface Circuits from Functional and Timing Specifications

摘要

In this paper the synthesis of asynchronous interface circuits from functional and timing specifications is discussed. We focus on timing analysis methods in order to use their results for a comprehensive synthesis process. Therefore we consider interval based timing constraints resulting from the system environment of such interface circuits into the well-known specification form of asynchronous circuits, called signal transition graphs (STG). As novel contributions, we propose general methods to analyze timing constraints according to specific firing rules in cyclic STG. A new synthesis procedure that exploits the results of the timing analysis in order to produce reduced logic implementations is introduced. Results are presented to establish the precedence relation of transitions, which is important in consideration of the synthesis process of asynchronous communication protocols. Synthesis results of time asynchronous circuit specifications demonstrate considerable advantages of this approach compared with other methods. All algorithms and methods presented in this paper have been integrated in an object-oriented graphical design environment. This system provides links with existing state of the art asynchronous and synchronous circuit synthesis tools and implements a consistent design methodology for asynchronous circuit engineering.