Logic circuits dynamic parameters analysis methodology

摘要

This paper presents a compact and simple procedure applicable to combinational logic circuits for timing analysis. We follow established guidelines but shall define new variables (time-dependent logic variables-TDLVs) that will improve the efficiency of the previously mentioned procedures. By using the methodology suggested we shall substitute a very laborious technique (pure delay circuit + time constant method) with a simpler procedure that will pinpoint the specific conditions for the logic circuit's anomalous behaviour, within a few steps. The conclusion can be drawn that only a strictly limited number of situations should be considered-in conjunction with the function that is being implemented by the circuit analysed.