机译:片上内存网络拓扑互连长度的动力感知高级评估模型
School of Computer Science and Technology Beijing Institute of Technology Beijing;
School of Computer Science and Technology Beijing Institute of Technology Beijing;
School of Computer Science and Technology Beijing Institute of Technology Beijing;
School of Computer Science and Technology Beijing Institute of Technology Beijing;
School of Computer Science and Technology Beijing Institute of Technology Beijing;
School of Computer Science and Technology Beijing Institute of Technology Beijing;
power evaluation; on-chip memory network topology; NoC interconnects; IPETOM;
机译:片上内存网络拓扑互连长度的动力感知高级评估模型
机译:用于可靠的VLSI片上时钟延迟评估的多级寄生互连电容建模和提取
机译:用于可靠的VLSI片上时钟延迟评估的多级寄生互连电容建模和提取
机译:使用网络演算的片上互连的分析建模和评估
机译:多层环境中波长路由IP / MPLS网络的光路拓扑配置:集成模型,算法和分析。
机译:用网络科学方法对供应链网络的拓扑和鲁棒性进行建模:回顾与展望
机译:具有密集片上网络的多核体系结构的六边形处理器和互连拓扑