Hardware Implementation of NoC based MPSoC Prototype using FPGA

摘要

The work presented in this paper concerned with the design and hardware implementation of the Network on Chip based Multi- Processing System on Chip prototype. The design process is performed using Very High speed integrated circuit Hardware Description Language (VHDL) and simulated using ISE 14.1 software package. The structure of the Network on Chip (NoC) considered in this paper is a two dimension (2D) mesh topology network which consists of 3 by 3 nodes. Each node consists of three components, these are, Processing Element (PE), Network Interface (NI) and Router (R). The nodes of the proposed network were divided into master and slave nodes, while each type has its own PE and NI; the router performs the same function in two types. The core of each node is the router which is responsible for directing the data from the source to the destination, therefore and in order to reduce the complexity of the network as well as the gate count, a minimized structure of the router has been designed and implemented. The target device was Spartan 3AN-XC3S700AN FPGA with utilization of low gate count. Simulation process performed with clock frequency of 82.734 MHz and the results show promising performance of the proposed network. The complete NoC system has been tested in real time and the experimental results confirmed validity of the design as well as the simulation results.