Advanced Testing Methods for Reversible Logic

摘要

Testing is an essential step that ensures the designed circuit realizes desired functionality. Testing an integrated circuit is the time-consuming task nowadays. Different methods are needed to get shorter test time. This paper presents an original approach and a practical system for implementation and testing of reversible logic. These testing methods, based on DFT (Design for testability) techniques. Reversible ALU is a testing circuit in this process. This ALU is tested by using two techniques of DFT which improves the controllability and observability of internal nodes, so that embedded functions can be tested. A node is said to be testable if it is easily controlled and observed. The techniques are 1) Ad hoc method and 2) Simple BIST (Built-in self-test) method, BIST belongs to the structured technique of DFT. This design is with Verilog HDL and simulated using ISIM simulator and implemented on Spartan3E (XC3S500E-FG320-5) FPGA. This proposed designed architecture provides delay of 41.054ns for Simple BIST and 40.774ns for Ad-hoc test methods, with an area coverage of 7% and 5% on Spartan 3E implemented by using Xilinx ISE Design Suite.