design for testability; logic arrays; logic testing; logic gates; fault simulation; low-power electronics; design for test; fault models; iterative logic arrays; reversible circuits; testability; universal test sets; low-power circuits; quantum computation; k-wire controlled NOT gates; single stuck-at fault; multiple stuck-at fault; AND gate; EXOR gate; Reed-Muller circuits; single cell fault;
机译:可逆电路通用测试仪
机译:可逆电路通用测试仪
机译:可逆电路通用测试仪
机译:用于通用测试集的可逆电路综合测试以及可逆迭代逻辑阵列的C-可测试性
机译:可逆逻辑中的综合,测试和容差
机译:一种使用QCA实现具有成本效益的算术逻辑电路的新型可逆逻辑门及其系统方法
机译:使用可逆逻辑构造在线可测试电路