Comparison and Performance Analysis of Various Low Power Digital design Techniques

摘要

The integrated circuits have gone through extensive phase of development in past few decades. This had given enormous impetus to the field of IC based technology. However, the battery of the systems has not evolved in the same pattern and made researchers to look for development of techniques based on the theme of low power design. In this paper comparison of various techniques for low power digital design is done in terms of various design metrics. As static power dissipation is one of main problems at sub-nanometer regime especially below 65 nm in CMOS where it contributes almost 80 percent of total power dissipation. The novel stacking techniques are applied at 0.13μm to overcome static power dissipation as well as improve figure of merit. The same stacking techniques are also applied at lower technology node such as 45nm and the effect of power, delay is measured with change in width as well as technology node. The results are compared on the basis of figure of merit. The comparison of other novel techniques that are implemented on 1-bit full adder circuit are GDI where GDI is used as multiplexer to implement 1-bit Full adder is also presented. The comparison of all the techniques is done in terms of design metrics. The novelity of this work is that comparison is made amongst various techniques that will be a very useful tool for optimization of power for application specific digital circuits.