Design of Complex IEEE Floating Point Multiplier for FFT Applications

摘要

The DFT (Discrete Fourier Transform) is the family of Fourier transform and most important discrete transform, used to perform Fourier analysis in digital signal processing. DFT is purely discrete (i.e) discrete-time data sets are converted into a discrete-frequency representation. This is in contrast to the DTFT that uses discrete time, but converts to continuous frequency. DFT is implemented by FFT (Fast Fourier Transform) which accelerates and perform the DFT process in an efficient and optimal way. For this reason DFT is used in partial differential equations, convolutions, data compression, polynomial multiplication etc. Multipliers play a major role in almost all DSP application. There is a requirement of efficient complex multiplier, since most of the digital signal processes involves operations on complex numbers. Hence a design of floating point multiplier (one of complex multiplier used to multiply floating numbers) for FFT processor using CSD (canonical signed digit) technique is being proposed in this paper. The design is analyzed and simulated by Quartus II v9.1. The proposed system improves speed, accuracy.