An Efficient Multichannel FIR Filter Architecture for FPGA and ASIC Realizations

摘要

In this paper, a Time division multiplexing (TDM) based multichannel FIR filter architecture is proposed using a single multiplier and adder irrespective of number of channels and taps using the concept of resource sharing principle. For efficient optimization of the resources Output Product Coding (OPC) and Dual port schematic is used, which are based on Look-Up-Table (LUT). The proposed 16-tap multichannel architecture is implemented using Verilog Hardware Description Language (HDL) and synthesized in Xilinx Vertex Field Programmable Gate Array (FPGA). The results obtained from the single channel FIR filter architecture, the frequency of the system supports up to 480 MHz with reduced area. The cell level performance is also obtained using Cadence RC compiler with TSMC 180 nm CMOS technology.