In this paper, the proposed method use an optimized architecture based on Distributed Arithmetic-Offset Binary Code (DA-OBC) technique. In this architecture, combination of both Look-up Tables (LUTs) and multiplexers (MUXs) are used for computational purposes. The validity of the proposed method is demonstrated by implementing a 16th-order inner product in the form of Finite Impulse Response (FIR) filter on different FPGAs. The performance results for number of LUTs, maximum frequency and dynamic power consumption are consistent across different FPGA devices. It is observed that the proposed architecture has dynamic power savings of 7.51% and 13.50% compared to existing With LUT and Without LUT architectures respectively on Spartan 6. While on Spartan 3A, the proposed architecture has dynamic power savings of 8.83% and 15.28% compared to With LUT and Without LUT architectures respectively. Moreover, the proposed architecture has appreciable resource savings advantage compared to the existing architectures.
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