Method and apparatus for high-speed CRC computation based on state-variable transformation

摘要

A method, and a system for employing the method, for computing a cyclic redundancy code (CRC) of a communication data stream taking a number of bits M at a time to achieve a throughput equaling M times that of a bit-at-a-time CRC computation operating at a same circuit clock speed. The method includes (i) representing a frame of the data stream to be protected as a polynomial input sequence; (ii) determining one or more matrices and vectors relating the polynomial input sequence to a state vector; and (iii) applying a a linear transform matrix for the polynomial input sequence to obtain a transformed version of the state vector. The method can further include (iv) applying a linear transform matrix to the transformed version of the state vector to determine a CRC for the polynomial input sequence, if the communication data stream is received by a network device. The method can further include (v) appending the CRC as a frame check sequence (FCS) to the communication data stream for detection by a receiving device.