Using Codes with Summation of Weighted Bits to Organize Checking of Combinational Logical Devices

摘要

This article analyzes the peculiarities of applying weighted sum codes in tasks of building logical device check circuits for weighing of bits via random weighting coefficients, with check bits limited in number by the number of check bits of classical Berger codes. Important regularities typical of weighted sum codes are discovered. Weighted codes belong to codes that detect unidirectional errors (UED codes). The presented technique of synthesizing weighted sum codes allows creating the simplest structures of these devices based on the standard circuits of full adders and half adders of units. The main properties of weighted sum codes via error detection in information vectors and in outputs of combinational check circuits are confirmed via experiment.