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Performance analysis of low power LNA using particle swarm optimization for wide band application

机译:宽带应用粒子群优化低功率LNA性能分析

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This paper characterizes a design analysis of low power (LP) and low voltage (LV) optimized low noise amplifier (LNA) for wide band applications. With review discussion on design challenges of LP and LV, a new biasing metric has been introduced for radio frequency analog circuit. The proposed LNA consists of two stages, the first stage is a current reuse topology, in which a combination of PMOS transistor stack on top of NMOS transistor has been used with series inductive peaking in the feed-back loop. It helps a lot to achieve the target of LP and LV, while the second stage is a mutually coupled CS stage, used for wideband matching to enhance the bandwidth and noise figure (NF). For optimization of passive component parameters of proposed LNA, particle swarm optimization (PSO) algorithm has been used. All the simulations have been done for a range of frequency 0-35 GHz in Cadence Virtuoso software 45-nm CMOS technology. The results quoted 18.57 dB maximum voltage gain, 2.4 dB NF, 17.1 dB S-11, 16.6 dB S-21, at frequency 25.4 GHz with 0.8 V, 1.6 mW broad band LNA. (C) 2019 Elsevier GmbH. All rights reserved.
机译:本文表征了用于宽带应用的低功率(LP)和低电压(LV)优化的低噪声放大器(LV)的设计分析。通过审查讨论LP和LV的设计挑战,已引入新的偏置度量,用于射频模拟电路。所提出的LNA由两个阶段组成,第一阶段是电流重复使用拓扑,其中PMOS晶体管堆叠在NMOS晶体管顶部的组合已经与馈回环中的串联电感峰值一起使用。它有助于实现LP和LV的目标,而第二级是相互耦合的CS级,用于宽带匹配以增强带宽和噪声图(NF)。为了优化所提出的LNA的无源分量参数,已经使用了粒子群优化(PSO)算法。所有仿真都是在Cadence Virtuoso软件45-NM CMOS技术中的一系列频率0-35 GHz。结果引用18.57dB最大电压增益,2.4 dB NF,17.1dB S-11,16.6 DB S-21,频率为25.4GHz,宽带LNA为0.8 V,1.6兆瓦。 (c)2019年Elsevier GmbH。版权所有。

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