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首页> 外文期刊>ACS applied materials & interfaces >Damage-Free Back Channel Wet-Etch Process in Amorphous Indium-Zinc-Oxide Thin-Film Transistors Using a Carbon-Nanofilm Barrier Layer
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Damage-Free Back Channel Wet-Etch Process in Amorphous Indium-Zinc-Oxide Thin-Film Transistors Using a Carbon-Nanofilm Barrier Layer

机译:使用碳纳米膜势垒层的非晶铟锌氧化物薄膜晶体管的无损背沟道湿蚀刻工艺

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摘要

Amorphous indium-zinc-oxide thin film transistors (IZO-TFTs) with damage-free back channel wet-etch (BCE) process were investigated. A carbon (C) nanofilm was inserted into the interface between IZO layer and source/drain (S/D) electrodes as a barrier layer. Transmittance electron microscope images revealed that the 3 nm-thick C nanofilm exhibited a good corrosion resistance to a commonly used H3PO4-based etchant and could be easily eliminated. The TFT device with a 3 nm-thick C barrier layer showed a saturated field effect mobility of 14.4 cm2 V-1 s~(-1), a subthreshold swing of 0.21 V/decade, an on-to-off current ratio of 8.3 X 10~(10), and a threshold voltage of 2.0 V. The favorable electrical performance of this kind of IZO-TFTs was due to the protection of the inserted C to IZO layer in the back-channel-etch process. Moreover, the low contact resistance of the devices was proved to be due to the graphitization of the C nanofilms after annealing. In addition, the hysteresis and thermal stress testing confirmed that the usage of C barrier nanofilms is an effective method to fabricate the damage-free BCE-type devices with high reliability.
机译:研究了具有无损伤背沟道湿法刻蚀(BCE)工艺的非晶铟锌氧化物薄膜晶体管(IZO-TFT)。将碳(C)纳米膜插入IZO层和源/漏(S / D)电极之间的界面作为阻挡层。透射电子显微镜图像显示,厚度为3 nm的C纳米膜对常用的H3PO4基蚀刻剂表现出良好的耐腐蚀性,并且可以轻松消除。具有3 nm厚C势垒层的TFT器件的饱和场效应迁移率为14.4 cm2 V-1 s〜(-1),亚阈值摆幅为0.21 V /十倍,通断电流比为8.3。 X 10〜(10),阈值电压为2.0V。这种IZO-TFT的良好电性能是由于在反向沟道蚀刻工艺中保护了插入的C至IZO层。而且,证明了器件的低接触电阻是由于退火后C纳米膜的石墨化。此外,磁滞和热应力测试证实,使用C势垒纳米膜是一种制造具有高可靠性的无损伤BCE型器件的有效方法。

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