Measurement and Analysis of Delay and Power Variations in 90nm CMOS Circuits

摘要

As the transistor size shrinks, process variations increase. Under the existence of the variations, an existing design flow will not be effective for minimizing the worst-case circuit delay and average power consumption. As the first step toward developing a better solution, this paper investigates basic characteristics of the delay and the power variation. We measured delay and power consumption values for 1,890 ring oscillator circuits designed with 90nm CMOS technology. We also analyzed both intra-chip and inter-chip variations for delay, dynamic power consumption and leakage power consumption. The measurement results demonstrated that the leakage power variation is very large and the inter-chip variations are larger than the intra-chip variations.