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首页> 外文期刊>電子情報通信学会技術研究報告. VLSI設計技術. VLSI Design Technologies >Fault tolerant datapath based on algorithmic redundancy and voting
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Fault tolerant datapath based on algorithmic redundancy and voting

机译:基于算法冗余和投票的容错数据路径

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摘要

In this paper, we propose a combination of triple algorithmic redundancy and vote-and-writeback configuration for realizing concurrently error correctable RT-level datapath of a specified computation algorithm. The vote-and-writeback configuration would contribute to reduce wire complexity around voters, compared with other conventional voting scheme. When a register assigned for a voted data is faulty, the vote-and-writeback configuration can not correct erroneous voted data on this register. It is interesting that, even though, fault tolerance of the datapath with respect to single fault for any constituent of the datapath can be guaranteed by this vote-and-writeback configuration and appropriate insertion of voters.
机译:在本文中,我们提出了三重算法冗余和投票和回写配置的组合,以实现指定计算算法的并发纠错的RT级数据路径。与其他常规投票方案相比,投票和回写配置将有助于降低投票者周围的连线复杂性。当分配给表决数据的寄存器出现故障时,表决写回配置不能更正该寄存器上的错误表决数据。有趣的是,即使通过此投票和回写配置以及适当插入投票者,也可以保证数据路径相对于数据路径任何组成部分的单个故障的容错能力。

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