A floorplanning method for simultaneously determining module placement and global routes considering buffer insertion

摘要

This paper presents a floorplanning method for ULSI layout, which simultaneously determines the module placement as well as global routes with buffer-insertion and wire-sizing. The proposed method is based on simulated annealing, and is executed in three phases, in which the cost function to evaluate a floorplan is changed so that a good solution is obtained in a short computation time. To get a global route considering buffer insertion and wire-sizing, a global route of each net is evaluated by table look-up based on the positions of terminals of the net. Experimental results show that the proposed method is effective to obtain a good floorplan under the timing constraint.