Characteristics of Locally-Separated Channel FinFETs with Non-Overlapped Source/Drain to Gate for Sub-50 nm DRAM Cell Transistors

摘要

We proposed p{sup}+{sup}+ gate bulk FinFETs that has a locally seperate channel (LSC) and non-overlapped S/D to gate structure, and shown improved scalability. The key device characteristics were investigated by using extensive simulations, and the speed characteristics were studied with a non-overlap distance. For the non-overlap LSC FinFET structure, device characteristics with gate length (L{sub}g), channel fin width (W{sub}(cfin)) and non-overlap length (L{sub}(no)) were carefully investigated in terms of the drain induce barrier lowering (DIBL), off-state leakage current (I{sub}(off)), subthreshold swing (SS), and threshold voltage (V{sub}(th)). The non-overlap LSC FinFET structure showed improving DIBL and SS as L{sub}(no) increases. These results show that the non-overlapped S/D to gate structure is useful in suppressing the SCE by increasing effective channel length. We also obtained much lower I{sub}(off) and wider process margin compared to those of overlap LSC structure. The devices with an L{sub}(no) of longer than 0 nm give lower I{sub}(off) by -100 times than that of the device with an L{sub}(no) of-5 nm. As a result, we could achieve optimum non-overlap length about ～5 nm. The proposed structure had good I{sub}(on) /I{sub}(off) and DIBL characteristics compared to those of overlapped structure.