New Architecture for Multiple-Valued Fine-Grain Reconfigurable VLSI Based on Current-Mode Logic

摘要

This article presents a fine-grain reconfigurable VLSI based on multiple-valued X-net data transfer scheme. Two binary data can be transferred from two cells to one common adjacent cell simultaneously at each X intersection, which leads to area-efficient data transfer without reducing performance. Each cell is composed of a switch block and a logic block. Multiple-valued signaling is utilized to implement a compact switch block. In each logic block, differential-pair circuits are used to realize low-power logic operations including threshold operations, an arbitrary 2-variable binary function and a bit-serial addition. Moreover, a current-source sharing technique between a series-gating differential-pair circuit and a current-mode D-latch is utilized to reduce the current source count for low power. As a result, the area and power consumption of the multiple-valued reconfigurable VLSI is reduced to 60% and 82% in comparison with that of an equivalent CMOS reconfigurable VLSI, respectively, while the delay is kept same.