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CONFIGURATION MEMORY IMPLEMENTATION FOR LUT-BASED RECONFIGURABLE LOGIC ARCHITECTURES
CONFIGURATION MEMORY IMPLEMENTATION FOR LUT-BASED RECONFIGURABLE LOGIC ARCHITECTURES
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机译:基于LUT的可重构逻辑体系结构的配置内存实现
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摘要
A reconfigurable processing unit ( 1 ) is described which comprises, data flow controlling elements ( 10 ), data manipulating elements ( 20 ), a configuration memory unit ( 30 ) comprising a plurality of memory cells ( 31 a, . . . ) for storing settings of the data flow controlling elements ( 10 ) and an address decoder ( 40 ) for converting an address into selection signals for the memory cells ( 31 a, . . . ). The reconfigurable processing unit of the invention is characterized in that the address decoder ( 40 ) is shared between the configuration memory unit ( 30 ) and a further memory unit ( 20 ), or between two configuration memory units ( 30, 30 '). This provides for a reduction in memory area of the reconfigurable processing unit ( 1 ).
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