Simultaneous Calibration of RC Mismatch and Clock Skew in Time-Interleaved S/H Circuits

摘要

The RC mismatch among S/H stages for time-interleaved ADCs causes a phase error and a gain error and the phase error is dominant. This research points out that clock skew and the phase error caused by the RC mismatch have similar effects on the sampling error and then can be compensated with the clock skew calibration. Simulation results agree well with the theoretical analysis. With the phase error compensation of RC mismatch, the SNDR in 14b ADC can be improved by more than 15dB in the case that the bandwidth of S/H circuits is 3 times the sampling frequency.