A novel DRAM architecture for high-speed array operation with improved data retention characteristics

摘要

The improvement of data retention characteristics is always requisite for the development of DRAM. Although Boosted Sense Ground (BSG) scheme has been proposed as one of the solution, it has difficulties generating stable boosted sense ground and realizing fast sense operation, which should be settled in mass production. To clear up those problems in the conventional BSG scheme, this paper introduces a Precharged-Capasitor-Assisted Sensing (PCAS) scheme with a new level controller suitable for it. In addition, the measured result is presented to verify the validity of the PCAS scheme.