Worst-Case Analysis to Obtain Stable Read/Write DC Margin of High Density 6T-SRAM-Array with Local Vth Variability

摘要

The 6T-SRAM cells in the sub-100 nm CMOS generation are now being exposed to a fatal risk that originates from large local Vth variability (σ{sub}(V_Local)). In this paper, to achieve high-yield SRAM array in presence of random σ{sub}(V_Local) component, we propose a worst-case analysis that determines the boundary of the stable Vth region for SRAM read/write DC margin (Vth Curve) Applying this method to our original 65nm SPICE model, we show some characteristic behavior of the Vth Curve. Throughout this paper, we suggest new criteria to discuss SRAM array stability with Vth variability.