Trace-Driven Emulation of Large-Scale Networks-on-Chip on FPGAs

摘要

Research and development of large-scale Networks-on-Chip (NoCs) play a key role in designing future many-core systems but are challenging due to the lack of fast and accurate evaluation environments. In recent years, there have been several attempts to build NoC emulation systems using FPGAs. These studies have shown promising emulation speedups of up to several orders of magnitude compared with conventional software simulators. However, emulating large-scale NoCs with hundreds to thousands of nodes on FPGAs is a challenging problem because of the FPGA capacity constraints. Moreover, supporting trace-driven workloads captured from practical applications may drastically degrade the emulation speed, especially when the emulated NoC is large, because the trace data are typically very large and thus stored in off-chip memory (usually DRAM). In this paper, we first present estimates of the DRAM capacity and bandwidth required for emulating NoCs under trace-driven workloads. We next show that although the limitation of DRAM bandwidth can be alleviated by storing trace data to DRAM in order of the emulation cycle and sequentially loading them during the emulation, a cyclic dependency between trace data and the network may occur in some certain cases. Finally, we describe our approach to enable trace-driven emulation of large-scale NoCs on FPGAs. In our previous work, to overcome the FPGA capacity constraints, we have proposed an emulation method based on the time-division multiplexing technique where a NoC is emulated using a small number of physical nodes. In this work, we show that this emulation method also makes it much easier to achieve the DRAM bandwidth requirement when emulating large-scale NoCs under trace-driven workloads. We explain in detail how trace data are stored in DRAM and fed to the emulated NoC efficiently and show some preliminary evaluation results.