Buffer Management based on a Parallel and Pipeline Mechanism to Support 128×128 Photonic Packet Switches with 40Gbps Ports

摘要

We investigate a high-speed buffer management mechanism for output-buffered photonic packet switches. We propose a parallel and pipeline mechanism on multi-processing architecture for this purpose. The machanism provides N times faster processing than an existing 0(N) mechanism does, where N is the number of ports. Through hardware simulation after place and route operation, we confirm feasibility of an FPGA-based buffer management hardware for 8×8 photonic packet switches with 40Gbps ports, which is capable of asynchronously arriving variable-size packets, of which minimum is 64byte. A support of 128×128 packet switch with 40Gbps ports is also feasible by using our mechanism and a latest FPGA technology.