A Parallel and Pipeline Algorithm for Output-Buffer Management in Photonic Packet Switches -For a case of Synchronous, Fixed-Size Packets-

摘要

We investigate a high-speed buffer management mechanism for output-buffered photonic packet switches. We pro-pose an O(1) algorithm based on parallel and pipeline processing for this purpose. The proposed machanism provides N times faster processing than an existing O(N) mechanism does, where N is the number of ports. Through hardware simulation af-ter place and route operation, we confirm feasibility of an FPGA-based buffer management hardware for 8x8 photonic packet switches with 40Gbps ports, which is capable of synchronously arriving 64byte fixed-size packets.