A Hardware Neuronal Network Model of a Two-level Central Pattern Generator

摘要

This paper addresses hardware designs of a half-centered locomotor central pattern generator (CPG), composed of units reproducing the electrical behavior of neurons and synapses, such as action potentials, bursting discharges, and post-synaptic potentials. The typical phenomenon generated by the CPG is an alternating rhythmic activity of extensor and flexor sites, in the absence of external rhythmic input. In order to reproduce the deletion phenomena, or the phase resetting and non-resetting rhythmic activities observed after during spontaneous cessation of activity, a two-level CPG network and unit burst generators (UBGs) were proposed by Rybak et al. (2006) from the viewpoint of mathematical modeling. The deletion at the first level, i.e., the rhythm generator (RG) level, caused the post-deletion rhythm to be phase shifted (reset) with respect to the pre-deletion rhythm. However, the deletion at the second level, i.e., the pattern formation (PF) level, caused the post-deletion rhythm to be un-phase shifted (non-reset) with respect to the pre-deletion rhythm. This paper confirms that such deletion phenomena, or the phase resetting and non-resetting phenomena, could be well reproduced in the hardware design of a two-level CPG using the electronic circuit simulator SPICE. In particular, it has been clarified that non-resetting deletions appeared, even with the cessation of activity occurring at any phase with respect to the observed temporal bursting. Hardware synapse models, phenomenologically reproducing excitatory and inhibitory post-synaptic potentials (EPSP and IPSP), were newly designed in order to connect the hardware neuron models, proposed by Hoshimiya et al. (1979) for the excitable and/or oscillatory neuron, and by Maeda and Makino (2000) for the bursting neuron.