Self-reconfigurable mesh array on FPGA

摘要

A major issue in designing massively parallel computer is an efficient reconfiguration strategy to provide a fault tolerance mechanism to avoid defective processors. The most of previous reconfigurable algorithms of mesh array processor are not easily implemented in VLSI. We proposed a self-reconfigurable algorithm of mesh array for easily hardware implementation. The performance of the self-reconfigurable system shows that array yields are much improved than previous reconfiguration architectures. This paper address a self-reconfigurable mesh array implemented on FPGA and the hardware performance is also discussed in detail.