Modeling the Effective Capacitance of Interconnect Loads for Predicting CMOS Gate Slew

摘要

In deep submicron designs, predicting gate slews and delays for interconnect loads is vitally important for Static Timing Analysis (STA). The effective capacitance Ceff concept is usually used to calculate the gate delay of the interconnect loads. Many Ceff algorithms have been proposed to compute gate delay of interconnect loads. However, less work has been done to develop a Ceff algorithm which can accurately predict gate slew. In this paper, we propose a novel method for calculating Ceff of interconnect load for gate slew. The simulation results demonstrate a significant improvement in accuracy.