Saddle-fin Cell Transistors with Oxide Etch Rate Control by Using Tilted IonImplantation (TIS-Fin) for Sub-50-nm DRAMs

摘要

As DRAM cell pitch size decreases, the need for a high performance transistor is increasing. Though saddle-fin (S-fin) transistors have superior characteristics, S-fin transistors are well known to be more sensitive to process variation. To make uniform S-fin transistors, for the first time, we developed a new fin formation method using tilted ion implantation along the wordline direction after a recess gate etch. Due to the increased etch rate of the oxide film by ion implantation damage, fins are made at the bottom channel of the recess gate after wet etching. The resulting tilt implanted saddle-fin (TIS-fin) transistor has remarkably improved characteristics, such as 8% subthreshold swing (SS) and a 40% drain induced barrier lowering (DIBL) decrease. Especially, the TIS-fin with a neutral dopant has a reduced threshold voltage (Vth) variation within a wafer (< 100 mV), which is comparable with that of a mass-produced sphere-shaped recessed channel array transistor (SRCAT).