Implementation of 32 point FFT Processor Core in VHDL with Memory Optimization Technique

摘要

The paper focuses on implementation of 32 point FFT algorithm. FFT algorithm is one of the many methods used for the calculation of Discrete Fourier Transform (DFT). Butterfly structure is preferred for the calculation of DFT due to its symmetry and periodicity property which makes it suitable for hardware implementations, but it requires the loading of the twiddle factors for each stage repeatedly, which leads to inefficient use of memory space. To overcome this, the symmetry and periodicity property of the twiddle factors of different stages together reduces the number of memory references and the storage space due to twiddle factors, there in reducing the number of clock cycles needed for the complete implementation of the algorithm. Modelsim 10.2 (MXE) tool is used for functional and logic verification of each block. The Xilinx Synthesis Technology (XST) of Xilinx ISE 14.2i tool is used for synthesis of transmitter and receiver using Virtex-5 FPGA.