Implementation of low-power FFT processor cores using a novel order-based processing scheme

摘要

The authors present a novel order-based coefficient processing scheme for the realisation of low-power FFT processors. The scheme is based on the minimisation of the Hamming distance between successive coefficients fed to the butterfly. A distinct feature of the scheme that distinguishes it from conventional order-based schemes lies in the fact that either the real part of the coefficient or its two's complemented value is used for the minimisation of the Hamming distance between successive coefficients and hence the switching activity. The paper describes the scheme and its implementation, and provides results using a number of fully synthesised FFT processor cores. The results demonstrate that the switching activity is reduced by up to 53% for different FFT lengths compared to only 27% when conventional order-based processing is employed. This significant reduction in switching activity leads to power savings in the range of 25% to 1% for different FFT processor cores.