A programmable gain amplifier with digitally assisted DC offset calibration for a direct-conversion WLAN receiver

摘要

cancellation (DCOC) scheme for a direct conversion WLAN receiver. Implemented n a standard 0.13-μm CMOS process, the PGA occupies 0.39 mm~2 die area and dissipates 0.5 mW power from a 1.2 V power supply. By using a single loop single digital-to-analog converter (DAC) mixed signal DC offset cancellation topology, the minimum DCOC settling time achieved is as short as 1.6 μs with the PGA gain ranging from –8 to 54 dB in a 2 dB step. The DCOC loop utilizes a segmented DAC structure to lower the design complexity without sacrificing accuracy and a digital control algorithm to dynamically set the DCOC loop to fast or normal response mode, making the PGA circuit in compliance with the targeted WLAN specifications.