A 12 bit 100 MS/s pipelined analog to digital converter without calibration

摘要

A 1.8 V 12 bit 100 MS/s pipelined analog to digital converter (ADC) in a 0.18 μm complementary metal–oxide semiconductor process is presented. The first stage adopts a 3.5 bit structure to relax the capacitor matching requirements. A bootstrapped switch and a scaling down technique are used to improve the ADC’s linearity and save power dissipation, respectively. With a 15.5 MHz input signal, the ADC achieves 79.8 dB spurious-free dynamic range and 10.5 bit effective number of bits at 100 MS/s. The power consumption is 112 mW at a 1.8 V supply, including output drivers. The chip area is 3.51 mm~2, including pads.