Low-Power Circuit Techniques for Charge-Scaling Successive Approximation Register ADC Design

摘要

Charge-scaling (CS) successive approximation register (SAR) ADC's are widely used in low-power electronics design. A significant portion of CS-SAR ADC power consumption is due to charging the CS capacitor array. This paper presents circuit techniques to reduce the voltage swing, and hence the power dissipation, of the CS capacitor array during ADC operations. The proposed techniques allow the ADC voltage reference to be reduced from V_(REF) to V_(REF)/2 without sacrificing the ADC input range. When the ADC input is larger than V_(REF)/2, a voltage subtraction is first performed and subsequently the resultant voltage is converted. In addition to power saving, the proposed techniques reduce the size of the CS capacitor array by half. The impacts of the proposed voltage subtraction on ADC accuracies are analyzed and circuit techniques are presented to address the accuracy concerns. The effectiveness of the proposed solutions is validated via post-layout simulations. Finally, the power saving of the proposed techniques is demonstrated by analysis, Matlab simulation and post-layout circuit simulation for 10-bit CS-SAR ADC circuits based on a 0.13 μm CMOS technology.