Efficient Evaluation of Power/Area/Latency Design Trade-Offs for Coarse-Grained Reconfigurable Processor Arrays

摘要

The presented evaluation framework allows extremely fast but still accurate power, area, and latency characterization of different design alternatives in a multidimensional design space of highly parameterized coarse-grained reconfigurable processor arrays. For the first time, we propose to use a relational database system, managing table-based, probabilistic macro-models, constructed with the help of a new non-uniform parameter sampling technique for the average power estimation of corresponding processor arrays on the architectural level. This leads to power estimation speeds in the milliseconds range within 10% estimation error compared to a state-of-the-art commercial gate-level post-layout power estimator. Furthermore, our approach fully accounts for such important power reduction techniques, like clock gating and operand isolation, which are commonly ignored otherwise. The feasibility and accuracy were tested in several case study implementations in a commercial 90 nm standard cell library. Experimental results show a superior scalability of the proposed technique: heterogeneous 100-core coarse-grained processor array with ≈0.5×10~6 logic gates circuit complexity, implementing a signal processing algorithm, can be analyzed for power and area within less than a minute on a standard consumer PC. Since currently there exists no published architecture-level power/area estimation framework for coarse-grained, software-programmable architectures, our work tries to address this shortcoming.