Process Optimizaton of Polymetal(W/WN/Polysilicon) Gate and Its Impact on Dynamic Random-Access Memory Chip Performance in 0.14-#mu#m Technology

摘要

This paper summarizes the problems and solutions in the process integration and device and circuit performances of fully working, 256-megait, dynamic random-access memory (DRAM) chips employing poly-metal gate. In the circuit analysis, an anomalous decay of the electrical signal was observed as the signal proceeds through the delays. A circuit simulation suggested the presence of parasitic components in the gate tungsten/polysilicon interface. The experiments on the tungsten-electrode formation and metal-go-gate contact formation schemes confirmed the effects of the parasitic components when the scheme employing an in-situ formation of diffusion barrier is used. The search for a new cleaning chemical for the postgate etch process was also considered in the integration because it was found to significantly affect the data-retention characteristics. Finally, the temperature dependence of the data retention of the chips employing polymetal- and polycide-gates demonstrated the results to be quire comparable to each other.