Design of Nonlinear CA Based TPG Without Prohibited Pattern Set In Linear Time

摘要

This paper reports an efficient BIST solution for VLSI circuits. The solution is based on an on-chip Pseudo-Random Pattern Generator (PRPG) for the CUTs (Circuit Under Test) of a VLSI chip that may be accessed through a full or partial scan path. The test solution guarantees non-issuance of the test patterns declared prohibited to a CUT. An n-bit Test Pattern Generator (TPG), for any arbitrary value of n, has been designed in linear time around the nonlinear Cellular Automata (CA). Experimental results confirm the enhanced pseudo-random quality of the generated test patterns, avoiding prohibited patterns due to application of nonlinear CA.