New Noise Tolerance Improvement Techniques for Dynamic Logic Circuits

摘要

With the continuance of aggressive scaling in IC technology, integrated circuit noise tolerance has become a design concern of utmost impor- tance. In this paper domino-OR based noise tolerant dynamic circuit tech- niques are proposed. The merits of these techniques are adjudged by comparison with highly noise tolerant circuits available in literature. Results extracted from SPICE simulations of circuit performance in 70nm technology node are used for comparison. Noise immunity curve, ANTE, DANTE, PANTE, NANTE are considered as performance met- rics for estimating the noise tolerance. One of the proposed circuits results in 5.8X and 6X improvement in power and energy normalized ANTE respectively. The second technique proposed, offers highest noise immu- nity amongst the techniques considered.