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Method and apparatus for enhancing noise tolerance in dynamic silicon-on-insulator logic gates
Method and apparatus for enhancing noise tolerance in dynamic silicon-on-insulator logic gates
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机译:增强动态绝缘体上硅逻辑门的噪声容忍度的方法和装置
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摘要
A method and apparatus for enhancing noise tolerance in dynamic Silicon-On-Insulator (SOI) logic gates improves the performance of dynamic gates using SOI technology. In particular implementations of logic, the logic inputs can be used to enable a pull-up chain constructed from a plurality of transistors. This pull-up chain holds the preset voltage on the summing node of the dynamic logic gate while the logic inputs are in a combination where parasitic bipolar transistors in the input logic chains conduct. The pull-up chain prevents spurious operation of the logic gate due to the conduction of the parasitic bipolar transistors. The pull-up also prevents spurious operation due to charge sharing that occurs when a device in the logic chain is enabled while another device is disabled. The charge sharing occurs due to charging the diffusion capacitance of the device which is disabled.
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