FPGA-Based Hardware Acceleration on I/O-Bound Scientific Applications

摘要

Reconfigurable computing using Field Programmable Gate Arrays (FPGAs) is known for its superiority in floating point arithmetic. Scientific applications and long running server applications typically engage in huge amount of iterations of loops with or without loop dependencies over a set of floating point data that may not be loaded to memory as a whole. Therefore, it is inevitable to load partial data to memory and perform computation over the partial data. While accessing data, the CPU will be stalled and the process is called I/O-bound. With the increasing latency gap between CPU and memory, those computation paradigms have alluded to two design dimensions: data dependence elimination and memory latency hiding. In this paper, an FPGA-based computation model is proposed to improve performance in running applications that requires extensively memory accesses in a loop by utilizing the flexibility of the FPGA-based re-configurable architecture. First, an application will be parallelized by using blocking algorithms, each of which is then loaded to the FPGA on-chip memory. Each block will be operated in parallel and thus, the memory latency can be hidden in a manner that overlaps with the computation. The performance evaluation results in terms of representative I/O-bound applications are reported, of which the speedup can be up to 21.8 in running a parallelized blocking QR matrix decomposition algorithm on the proposed computation model.