FPGA-based Hardware Implementation of Compact AES Encryption Hardware Core

摘要

Most of current embedded applications need AES algorithm implementations of small size and low power consumption to assure safe information conveyance. In this article, we present the implementation of a compact ASE hardware encryption core that is suitable for resource-limited applications based on FPGA technology. The core has 8-bit data path structure and supports encryption with 128-bit keys. The core has been described using VHDL language. The simulation and synthesis results are obtained using ModelSim and Xilinx ISE software tools, respectively. This implementation is compared to the previously reported compact implementations in terms of speed, area, and consumed energy. The implementation results showed that the adopted design achieves significant reduction in area (up to 32.4%) and consumed energy (up to 66.7%). Also, it has a significant increase in speed by ratios ranging from 28.6% to 44.5%. This makes the adopted design more suitable for resource-limited embedded applications.