Fault-tolerant Design Techniques in A CMP Archiques in A CMP Architecture

摘要

Single-chip multiprocessor (CMP) combined with the fault-loleranl(FT) techniques offers an ideal architecture to achieve high availability on the basis of sustaining high computing performance FT design of a single-chip multiprocessor is described, including the techniques from hard-wart redundancy to software support and firmware strategy. The design aims at masking the influences of errors and automatically correcting the system states.