Reversible Logic Based All Zeros and All Ones Pattern Recognization Using Quantum Dot-Cellular Automata

摘要

In Nanocommunication network, QCA has promising functionality in designing digital logic circuit at nanometer scale. In digital communication, sequence or pattern recognizer has significant functionality for bit error testing procedure. Among several types of bit error test patterns, all ones pattern and all zeroes pattern are practical in signifying the certain bit error signals. Lofting device density caused high power dissipation by logic circuit. Reversible logic has fixed this increasing problem by dissipating very less heat. In this paper reversible all ones and all zeroes pattern recognizer has been proposed and QCA is exploited to achieve those circuit at nanoscale for the first time. Both pattern recognizer is designed in two several ways and then they are implemented by using QCA. Both designs encompass only Peres gate and Toffoli gate. Peres gate based all ones as well as all zeros pattern recognizer and Toffoli gate based all ones as well as all zeros pattern recognizer consumes quantum cost 15 and 12 respectively. Circuits are measured in terms of cells, areas, circuit cost and clocking. Evaluation of the proposed work with theoretical values established its operational efficiency.