An Active Silicon Interposer With Low-Power Hybrid Wireless-Wired Clock Distribution Network for Many-Core Systems

摘要

Due to the increasing interconnect delay caused by shrinking wiring dimensions, modern synchronous many-core systems are now facing critical issues. Particularly, the power budget to propagate high-frequency clock signals across the chip is limited. It becomes more challenging using conventional metallic interconnects to deliver a clock with low uncertainties across active dies. This article proposes a novel hybrid wireless-wired clock distribution network, which improves the performance of ON-chip clock distribution significantly. By using embedded wireless clock transmitter and receiver designs, because of the high fan-out feature of the wireless clock transmission, the overall clock delay, skew, and power have been reduced. The proposed hybrid clock distribution scheme is verified through a novel test circuit by using Arm Mali-G77 GPU as an example. Experimental results indicate that the proposed clock distribution network exhibits a significant global delay reduction of up to 28.8%. Also, for the best case scenario, a maximum of 46.7% and 17.7% reduction in clock skew and power consumption, are identified, respectively. Thus, our proposed approach offers a promising solution to clock distribution for many-core integrated circuits, especially for high-performance systems.