A High-Performance LDO Regulator Enabling Low-Power SoC With Voltage Scaling Approaches

摘要

Low-power system-on-a-chip (SoC) with multiple voltage domains often adopts voltage scaling approaches to optimize power usage while maintaining enough performance. Voltage regulators having flexible output configurability, fast transient response, and high-power noise rejection ability are indispensable for this application scenario. A low-dropout (LDO) regulator was proposed in this article to convert an input of 1.9-1.1 V to an output of 1.1-0.2 V with a 10-mV tuning resolution by raising the concept of programmable recursively divide-by-two resistor array (PRDTRA). A high gain-bandwidth main regulation loop of the proposed LDO regulator was accompanied by a transient acceleration (TA) path and a unity power noise gain generator to achieve a 28-mV output variation during 0-100-mA load transient test while keeping a 60-dB power supply rejection ratio (PSRR) over a frequency band of 0-1 MHz. Performance evaluations show the performance superiority of the proposed LDO regulator.