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首页> 外文期刊>IEEE transactions on very large scale integration (VLSI) systems >GH CORDIC-Based Architecture for Computing N th Root of Single-Precision Floating-Point Number
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GH CORDIC-Based Architecture for Computing N th Root of Single-Precision Floating-Point Number

机译:基于GH的CORDIC架构,用于计算单精度浮点数的第n根

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摘要

This article presents hardware implementation for computing arbitrary roots of a single-precision floating-point number. The proposed architecture is based on Generalized Hyperbolic COordinate Rotation Digital Computer (GH CORDIC) algorithm. Benefiting from the wide range of floating-point numbers, our design is able to compute the Nth root of a single-precision floating-point number. After implementation, a series of tests have been carried out, including accuracy, power consumption, performance comparison, and so on. Simulation results indicate that our proposed method is capable of calculating the Nth root of a positive single-precision floating-point number with a relative error of 10(-7) approximately and promises an error-flatten performance. Synthesized results from a design compiler under TSMC-40-nm CMOS technology show that our design can achieve the highest frequency of 2.38 GHz with the area consumption of mu m(2) and power consumption of 86.9573 mW.
机译:本文介绍了计算单精度浮点数的任意根的硬件实现。所提出的架构基于广义双曲坐标旋转数字计算机(GH CORDIC)算法。从广泛的浮点数中受益,我们的设计能够计算单精度浮点数的第n个根。实施后,已经进行了一系列测试,包括准确性,功耗,性能比较等。仿真结果表明,我们所提出的方法能够大致计算具有10(-7)的相对误差的正单精度浮点数的第n个根,并承担错误平坦的性能。 TSMC-40-NM CMOS技术下的设计编译器的合成结果表明,我们的设计可以实现2.38GHz的最高频率,穆米(2)的面积消耗和86.9573 MW的功耗。

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