机译:优化扫描闩锁的低能量
T. J. Watson Res. Center IBM Res. Div. Yorktown Heights NY USA;
flip-flops; CMOS logic circuits; logic design; circuit optimisation; low-power electronics; pipeline processing; logic simulation; integrated circuit layout; scannable latch optimization; low-power applications; latch design; flip-flop design; performance optimization methodology; data-switching factor; glitching activity; formal analytical approach; energy-performance space; hardware intensity balancing; processor pipelines; objective function selection; transistor size tuning; power dissipation; clock distribution; extracted netlist simulations; multibit datapath registers; low overhead scan mechanism; low-power level-sensitive scan mechanism; two-phase master-slave C/sup 2/MOS latches;
机译:优化可扫描闩锁以降低能耗
机译:优化可扫描闩锁以降低能耗
机译:在扫描电子显微镜中以优化的低和极低能量对标本进行成像
机译:用于低功耗应用的时钟策略和可扫描锁存器
机译:大容量/大面积碘化钠扫描分析离散低能伽马射线源,以评估土壤中的污染。
机译:双能计算断层扫描中低剂量扫描参数的优化显示前十字架韧带
机译:优化可扫描锁存器以实现低能耗